1. Field of the Invention
The present invention generally relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device such as DRAM (Dynamic Random Access Memory) which has a calibration circuit that adjusts impedance of an output buffer included in an output circuit.
Priority is claimed on Japanese Patent Application No. 2009-023657, filed Feb. 4, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
In a semiconductor device such as a DRAM, in order to execute high-speed data transfer, it is necessary to achieve an impedance adjustment in a transfer system to suppress distortion in data transfer waveforms due to reflection.
Such an impedance adjustment is performed by adjusting the impedance of an output buffer circuit with a calibration circuit.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2008-048361 discloses a technique of adjusting impedance of an output buffer in a calibration period which is 64 times the cycle of an external clock.
In general, a calibration circuit includes a calibration terminal (ZQ terminal) that is connected to a replica buffer circuit to which a plurality of transistors is connected in parallel and a comparator that compares a voltage appearing in the ZQ terminal with a reference voltage.
Then, an external resistor is connected to the ZQ terminal so as to determine a combination of transistors that goes well with the external resistor, and the result of combination (DQ driver code) is reflected in an output buffer forming an input/output circuit (DQ circuit), thus setting impedance of the output buffer to a predetermined value.
In order to determine the combination of the transistors forming the replica buffer circuit, a calibration period is required in which voltages are compared by a comparator or the constituent transistors are changed.
Since the calibration period depends on the cycle of the external clock, the calibration period may decrease when the frequency of the external clock increases. Therefore, it is difficult to perform the highly accurate impedance adjustment.
To solve this problem, a calibration method has been developed in which an oscillator circuit is operated not by the external clock but by an internal clock generated from the external clock, and a calibration circuit is operated by an output of the oscillator circuit.
On the other hand, in the method of performing calibration based on the output of the oscillator circuit, there may be a case that the calibration will not end within a predetermined period of time due to process variations, operation status, or the like.
Therefore, there was a problem in that when a READ or WRITE command is input from an external semiconductor device, for example a memory controller, during the calibration period, a change in DQ driver code may occur through the whole of a period of time when the input/output circuit is activated, whereby noise may be generated in an input and output signal of the input/output circuit.